White Electronic Designs Corporation (NASDAQ:WEDC) expanded its family of DDR2 SDRAM-based multi-chip packages (MCPs) with the launch of an 8Gb device. The SDRAM is organized as 128M x 72, packaged in a 16 x 22mm, 352mm2, 208 plastic ball grid array (PBGA). This package provides high-density memory for extended-environment embedded computing, such as that used in aircraft, communications and missiles.

Benefits include higher board density and routing advantages, with 56% more space savings and a 50% reduction in I/O count over a comparable FPBGA approach. Reduced trace lengths result in lower parasitic capacitance. Other advantages include lower weight and a 1mm pitch that allows for larger balls on the ball grid.

The 8Gb DDR2 SDRAM is a high-speed CMOS, dynamic random-access memory with pipelined, multibank architecture that allows for concurrent operation and provides high, effective bandwidth. Available at data rates of 667, 533 and 400 Mbs in commercial, industrial and military temperature ranges, this MCP provides an upgrade path for the 64Mx72 package that is used on applications such as integrated core processors and radar systems.

The WEDC family of DDR2 SDRAM-based products starts at a density of 256MB (2Gb) in x64 and x72 data width configurations and is designed to give customers a high density memory solution that also meets the wide data widths necessary for their applications. These high-speed memories use a 4ns-prefetch architecture with an interface that allows two data words to be transmitted per clock cycle.

WEDC has full design, fabrication and test capabilities for a wide variety of multi-chip system in a package, Commercial-Off-The-Shelf (COTS) memory, processors and combination MCPs for demanding applications. Additionally, these microelectronic products can be ruggedized and processed for tamper resistance.